Senior Verification Engineer

Contact: 6 Month +

Pay :$112/hr on w2

Location: 100% Remote

Remote - Candidate must be willing to locate to a Client Site if converted

Southern CA

Austin, TX

Key Responsibilities:

Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog) Develop verification methodologies and test benches for block and system-level verification Create and execute test plans, develop test harnesses, and implement coverage models Conduct timing analysis, noise analysis, and other signoff checks Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering Support lab integration and troubleshooting activities Resolve design issues and drive solutions for timing, congestion, and other implementation challenges

Basic Qualifications:

7+ years of experience in ASIC design and implementation

Bachelor's degree in Electrical Engineering,

Computer Engineering, or related technical discipline Experience with FPGA & ASIC design Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog)

Experience with Linux development environment

Experience with design verification and test bench development

Responsibilities:

• Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off.

• Translate design specifications into verification strategies, measurable coverage goals, and early identification of high-risk scenarios.

• Select verification methods for each problem, including constrained-random simulation, formal analysis, and directed testing.

• Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions.

• Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results.

• Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem, and SoC levels.

• Apply and build AI-assisted verification capabilities for stimulus generation, regression triage, and coverage analytics.

• Review testbench architecture and debug methodology, and mentor junior engineers in verification methodology.

Preferred Skills and Experience:

• Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field
• Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)
• Experience with Software-Defined Radio Architectures, ADC/DAC, and/or DSPs
• Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM) Strong object-oriented programming and scripting skills (Python, TCL, Perl)
• Experience with physical design flows and industry-standard EDA tools
• Experience with RTL2GDSII physical design and signoff flows Knowledge of deep sub-micron FinFET and CMOS technologies Experience with DFT/Scan/MBIST/LBIST methodologies Experience mentoring junior engineers

Medical, dental, and vision insurance are available to qualified candidates who meet eligibility requirements.

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